Technical Field
The disclosure relates in generally to a method for fabricating a semiconductor device, and more particularly to a method for fabricating a semiconductor device with a strained-silicon structure.
Description of the Related Art
With the progress of device miniaturization, enhancing carrier mobility and driving current of the metal-oxide-semiconductor (MOS) transistor has become an important issue. In order to improve the speed of the MOS transistor, a strained-silicon technique has been developed and is taken as a main solution to improve the performance of the MOS transistor.
One approach of the strained-silicon technique includes steps of applying a patterned silicon nitride (SiN) hard mask layer and a spacer formed on a gate of the MOS transistor serving as an etching mask to forming recesses in a silicon substrate on which the gate is formed, and applying a selective epitaxial growth (SEG) method to forming an epitaxial layer, such as a silicon-germanium (SiGe) layer, to fill the recesses.
Because the lattice constant of the epitaxial SiGe layer is larger than that of the silicon, such characteristic is employed to cause alteration to the band structure of the silicon in the channel region of the silicon substrate. Accordingly, the carrier mobility and the speed performance of the MOS transistor are improved.
However, the SiN hard mask layer typically has a Si-rich surface (due to the compositional properties of SiN layers) that may serves as a seed layer in the SEG process, numberless fall-on defects including SiGe with an average diameter ranging from 30 to 60 nanometers (nm) are ubiquitously formed on the SiN hard mask layer, so as to make the SiN hard mask layer having a haze surface.
With the progress of device miniaturization and the shrink of critical dimension (CD), the SiN hard mask layer may be thinned down. The fall-on defects may extend more likely passing through the SiN hard mask layer and landing on the spacer or the gate of the MOS transistor to cause a plurality of granular structures hardly to be removed by the subsequent SiN hard mask removing process. As a result the subsequent process performed on the gate for forming the MOS transistor may be restricted and the reliability of the MOS transistor may be adversely affected.
Therefore, there is a need of providing an improved method for fabricating the semiconductor device to obviate the drawbacks encountered from the prior art.